1. Field of the Invention
This invention relates to saturating voltage detection and prevention for use with saturable circuit elements such as high speed multistep/subranging analog to digital converters.
2. Description of the Related Art
An analog to digital (A/D) converter is a device designed to convert an analog waveform into a series of digital words. The input of such a device is generally a continuously varying voltage signal; the output is a multi-bit step voltage signal representing a digital output (ones and zeroes). Within an A/D converter the input signal is compared to multiple reference voltages at periodic time intervals (the sampling rate). These comparisons measure whether the input voltage is greater than or less than a series of reference levels, in total thereby producing an output which approximately describes the state of the varying input. Unlike the analog input which is continuous, the comparisons are characteristically quantized, and therefore have a finite resolution that corresponds to the size of the intervals between successive reference voltage levels.
An issue with analog to digital conversion is that the conversion process takes a finite amount of time, meaning that the sampling cycle cannot be set arbitrarily short to accommodate a high frequency input. There are many different types of converters with conversion times ranging from greater than one second (sampling less than once per second) to less than two nanoseconds. Different materials and designs for A/D converters are best suited for different operating speeds; the specific application typically defines the type of converter employed. Several different designs are described in Grebene, Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons, 1984, pages 835-866.
Parallel or simultaneous A/D converters are generally regarded as some of the fastest designs. They use separate comparators in parallel for each quantization step (as opposed to using the same comparators repeatedly with changing reference voltages, or multiple comparators in series). Parallel A/D conversion is capable of completing an entire conversion operation in one step, and thus is referred to as flash conversion. FIG. 1 illustrates the basic design of an N-bit flash converter.
In the flash A/D converter shown in FIG. 1, an analog input is provided at terminal 2 and is transmitted to the variable inputs of a series of comparators 4 (there are 2.sup.N -1 comparators in an N-bit flash converter). A reference voltage is maintained across a series of resistors 6 from positive V.sub.ref terminal 8 to negative V.sub.ref terminal 10. These resistors 6 provide the step interval reference voltages which are applied to the reference inputs of the comparators 4. Comparators 4 compare their reference and variable input signals at time intervals determined by a sampling signal applied at terminal 12. The outputs of the 2.sup.N -1 comparators are combined by a decode logic subcircuit 14 to generate an N bit digital word.
To increase converter resolution with minimal increases in die area and power requirements, multiple flash converters may be combined. One such assembly is the multi-step/subranging converter. A conventional multistep/subranging converter, shown in FIG. 2, divides the conversion process into two steps. An analog input is supplied at input terminal 16 and directed to a track and hold element 18. The output of the track and hold is directed to both a summing amplifier 20 and the input of a first flash converter 22. The flash converter 22 generates an output which forms the first digits (in this case 4 bits) of the digital output word. This output is transmitted to a digital-to-analog (D/A) converter 24, which converts it back into an analog signal. The analog signal output of the D/A converter 24 is directed to a summing amplifier 20 which compares it with the original input, producing a residue signal that contains the finer details of the input information not resolved by the first conversion. The residue signal is then directed to a second flash converter 26 for finer quantization. The output of the second flash converter 26 is the second half of the digital output word. If the residue signal doesn't fall exactly in the voltage range of the second flash converter, however, that converter cannot function properly and missing codes result. The residue signal is often amplified. The amplication of the residue signal increases the effective sensitivity of the second converter to overvoltage signals.
Many of the fastest A/D converters utilize bipolar junction transistors (BJTs) for their high speed capabilities. When a BJT is subject to an overvoltage it is driven out of its linear operating range into saturation. Thus the flash converters 22 and 26 are especially susceptible to overvoltages. Even if the overvoltage is mild, a BJT driven out of its linear operating range into saturation requires time to recover. The recovery time is partially dependent upon the magnitude of the overvoltage, but it is often more than several conversion cycles. Extreme over-voltages can permanently damage the converter. During saturation, missing or incorrect codes often occur.
In the prior art, such overvoltage problems were remedied with input diode clamps, e.g., Schottky diodes. An example of a prior overvoltage protection design is shown in FIG. 3a. A pair of diodes 28 and 30 respectively have their anode and cathode connected to the analog input terminal 32 of the A/D converter 34. The opposite ends of diodes 28 and 30 are connected to different voltage references 36 and 38 which are respectively illustrated as ground and a negative voltage V.sub.ref. The different voltage references together define the limits of a range of input signals which may be transmitted to the A/D converter. When the input signal is not in the defined range one of the diodes (the diode corresponding to the range limit which is being exceeded) clamps the circuit.
With an ideal circuit, it would be possible to set the diodes' clamping voltages exactly equal to the extreme limits of the desired input range. In practice, however, diodes are not able to switch from open to conductive (clamping the circuit) abruptly within arbitrarily narrow voltage ranges. FIG. 3b illustrates the operation of a pair of typical diodes 28 and 30, having a forward bias breakdown voltage of 0.6 volts in controlling the voltage V.sub.ADC applied to the input of the A/D converter 34 as a function of an attempted input voltage V.sub.in. Three distinct types of response are evident: (1) linear conduction in region 40 which corresponds to input voltages well within the limits of the conduction range, (2) constant secure clamping, in regions 42 and 44, which corresponds to input voltages well beyond the limits of the conduction range, and (3) non-linear response, in regions 46 and 48, which corresponds to input voltages near a limit of the conduction range (near a clamping voltage of one of the diodes). Without an abrupt open to conductive transition, clamp level selection involves a trade-off between protecting the BJTs from saturating overvoltages, and preserving a linear operation. Selecting a clamp level that securely clamp before the input put voltage has reached a level which saturates the BJTs results in a non-linearity that distorts the extremes of acceptable input. Conversely a clamp voltage that ensures a completely linear operation involve a diode activating forward voltage drop which exceeds the voltage necessary to saturate the BJTs.
Preserving linearity is usually of paramount importance. Departing from a linear operating range causes the converter's digital output to vary from the input signal. Furthermore, when the BJTs do return to a linear range it is necessarily from an extreme voltage level, which further delays ideal response and increases the duration of false outputs. The result of the trade-off is thus typically to preserve linearity at the cost of the transistor saturation.